Click on “Optimization” -> “Area Optimization” Choose the optimization options and click “OK”
Step 4: Compiling and Modeling the RTL Code Once you have composed the RTL code, you need to assemble and run it to ensure that it is correct. synopsys design compiler tutorial
Launch Design Compiler Click on “File” -> “Open” and choose the RTL file Click on “Synthesis” -> “RTL Synthesis” Choose the optimization options and click “OK” Compile the RTL code using the vcs command
Step 4: Processing and Simulating the RTL Code Once you have composed the RTL code, you require to compile and simulate it to ensure that it is proper. Click on &ldquo
Step 5: Synthesizing the RTL Code After verifying that the RTL code is correct, you can synthesize it using Design Compiler.
Compile the RTL code using the vcs command Run simulation using the vcs command
Make a new file with a .v or .vhdl extension Write the RTL code using Verilog or VHDL Archive the file